1. Field of the Invention
The present invention relates to a burn-in socket used for carrying out a burn-in test for semiconductor chips in order to supply an assembly step with defect-free semiconductor chips whose reliability has been confirmed and, more particularly, to a burn-in socket used for carrying out a burn-in test for bare semiconductor chips.
2. Description of the Related Art
A burn-in test for semiconductor chips is usually carried out prior to an assembly step for assembling a module or the like. This burn-in test is intended to check, by applying heat and bias to each semiconductor chip, whether the semiconductor chip operates normally or not to find a defective chip at the initial stage.
A conventional burn-in test has been performed for semiconductor chips which are packaged in plastics and ceramics, which are in the TCP (Tape Carrier Package) state, etc. Only the defect-free semiconductor chips whose reliability has been confirmed, are screened and supplied to an assembly step in the packaged state.
The packaged semiconductor chips, which have been subjected to the burn-in test, are larger than bare chips. These semiconductor chips are therefore unsuitable for small-sized and thin devices such as a multi-chip module and an IC card which require a high-density mounting technique.
If a semiconductor chip is considered to be defective by the burn-in test, its manufacturing cost including the packaging cost is completely meaningless, resulting in increasing the cost of defect-free semiconductor chips.
To resolve the above problem, a technique of carrying out a burn-in test for bare chips and supplying defect-free chips in a bare state, is proposed. According to this technique, the burn-in test is carried out using a socket in which the bare chips are to be inserted.
For example, as shown in FIG. 1, the socket used for the burn-in test includes a lower container 101 and an upper container 102 formed of ceramics or the like.
The lower container 101 includes a recess 101a in which a semiconductor chip 103 for the burn-in test is set in a bare state. A wiring substrate 105 is provided at the bottom of the recess 101a with insulating paste interposed between them, and has a plurality of projecting electrodes 104 corresponding to chip electrodes (not shown) of the semiconductor chip 103.
Internal electrodes 107 are arranged around the recess 101a of the lower container 101. The wiring substrate 105 is electrically connected to the internal electrodes 107 through wires 108, and external electrodes 106 extending from the undersurface of the lower container 101, are connected to the internal electrodes 107.
The upper container 102 is provided with a presser 109 constituted by an aluminum block or the like. The presser 109 presses on the semiconductor chip 103 set in the recess 101a of the lower container 101 to bring the chip electrodes into contact with the projecting electrodes 104 arranged on the wiring substrate 105.
The presser 109 is movably mounted on the upper container 102 with an elastic member (rubber) 110 interposed between them and its pressure is controlled by a pressure control ring 111.
Using the socket described above, the burn-in test for the semiconductor chip 103 is carried out as follows.
First the bare-state semiconductor chip 103 is placed in the recess 101a of the lower container 101 with the chip electrodes downward. Then the upper container 102 is closed (or fixed onto the lower container 101), and the semiconductor chip 103 is pressed by the presser 109, with the result that the chip electrodes and projecting electrodes 104 are brought into reliable contact with each other. In this state, the semiconductor chip 103 is heated at a predetermined temperature and receives a signal for actually operating the semiconductor chip 103 from the external electrodes 106, thereby confirming the reliability of the semiconductor chip 103 or determining whether the chip 103 is defect-free or defective.
Another socket (not shown) can be used to carry out the burn-in test. In this socket, a semiconductor chip is placed in a container with chip electrodes upward, and probes mounted on the cover of a container are set so as to correspond to their respective chip electrodes.
However, the foregoing sockets have a drawback wherein the costs for forming the projecting electrodes 104 and the probes increase as the pitch between adjacent chip electrodes becomes narrower and narrower. In other words, the narrower the pitch between adjacent chip electrodes, the more difficult the formation of the projecting electrodes 104 and probes, and the higher the costs of the sockets themselves.
The socket with the projecting electrodes 104 has a drawback wherein the service life of the projecting electrodes 104 is relatively short.
The socket with the probes has a drawback wherein the probes are difficult to align with the chip electrodes.
As described above, in the socket used for carrying out the burn-in test for the bare-state semiconductor chips, the cost of the socket itself is increased, as is the operation cost required for the burn-in test, resulting in increasing the cost of defect-free semiconductor chips.